module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);

    wire cin;
    wire [3:0] cout;

    adder1 inst_adder0 (x[0], y[0], cin, cout[0], sum[0]);
    adder1 inst_adder[3:1] (x[3:1], y[3:1], cout[2:0], cout[3:1], sum[3:1]);

    assign sum[4] = cout[3];

    // This circuit is a 4-bit ripple-carry adder with carry-out.
	//assign sum = x+y;	// Verilog addition automatically produces the carry-out bit.

	// Verilog quirk: Even though the value of (x+y) includes the carry-out, (x+y) is still considered to be a 4-bit number (The max width of the two operands).
	// This is correct:
	// assign sum = (x+y);
	// But this is incorrect:
	// assign sum = {x+y};	// Concatenation operator: This discards the carry-out

endmodule

module adder1( 
    input a, b, cin,
    output cout, sum );

    assign{cout,sum} = a + b + cin;

endmodule
